Integrated circuits (ICs) have become the backbone of modern consumer electronics. The increased demand for functionality of consumer electronics has forced the complexity of IC's to skyrocket. In a number of applications, ICs are highly functional, low cost and have low power consumption. These demands create increased complexity on the design, verification, and manufacture of ICs.
A typical integrated circuit design may involve the creation of electronic components, such as transistors and resistors, and the interconnections of these components onto a substrate, such as silicon. The simulation, verification, and sometimes layout of these components usually is accomplished in sub-blocks, or modules. Each block may be simulated and verified individually. Multiple design teams typically work on the individual blocks. During the design process, before semiconductor manufacturing, it is desirable to verify the functionality of an integrated circuit design to be sure that it works substantially as expected. This process may be referred to as functional verification of an integrated circuit design.
Functional verification involves the verification that the design conforms to the specification. Functional verification may involve the validation that a design meets the desired functionality. Part of the process of verification includes the creation of a Register Transfer Level (RTL) representation of the digital circuit designs (RTL design) that describe in detail the functionality of the device or block at every cycle of the clock. Creation and verification of the RTL design may be one of the more difficult portions of the design process. In many instances, this verification is a very difficult and time intensive task. Simulation tools are typically used to assist in verification. In some designs, simulation-based functional verification is performed on multiple machines in parallel. During the verification process coverage data is produced that indicates which portions of the functionality and/or code have been tested.
Coverage in the verification cycle of digital designs was previously performed using a very simple flow and was restricted mainly to using code coverage. In the simplest flow, shown in background FIG. 1, a design under verification (DUV) is stimulated using multiple test-benches and a coverage database is generated for the DUV for each simulation run. Once all the simulations have been run, the coverage databases obtained from each run are merged together to get a comprehensive view of the coverage obtained from the entire verification.
If the design under verification (DUV) is identical across all the simulation runs, a merge of coverage databases is straightforward since the design hierarchy and the set of coverage points is identical. In practical usage, this is not the case. Multiple design teams work on different blocks of a chip design. Different configurations of a chip may be run with different simulations. As part of user methodology, different simulation runs of the same design have different modules at different levels of abstraction. For example, one level of abstraction may contain modules written in a higher level language, such as system C, while another may be written in a low level language such as a Hardware Description Language (HDL). As multiple design teams work on various parts of a design and the design evolves over time, both the design hierarchy (affecting code coverage) and the functional coverage points (affecting functional coverage) undergo changes. It may not be easy to get an overall view of coverage results for a chip design with different simulations, different coverage points, and different hierarchies.